434 lines
14 KiB
C
434 lines
14 KiB
C
/*
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nrf24l01 lib 0x02
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copyright (c) Davide Gironi, 2012
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Released under GPLv3.
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Please refer to LICENSE file for licensing information.
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*/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <util/delay.h>
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#include <string.h>
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#include <stdio.h>
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#include "nrf24l01.h"
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#include "nrf24l01registers.h"
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//include spi library functions
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#include NRF24L01_SPIPATH
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//address variables
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static uint8_t nrf24l01_addr0[NRF24L01_ADDRSIZE] = NRF24L01_ADDRP0;
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static uint8_t nrf24l01_addr1[NRF24L01_ADDRSIZE] = NRF24L01_ADDRP1;
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static uint8_t nrf24l01_addr2[NRF24L01_ADDRSIZE] = NRF24L01_ADDRP2;
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static uint8_t nrf24l01_addr3[NRF24L01_ADDRSIZE] = NRF24L01_ADDRP3;
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static uint8_t nrf24l01_addr4[NRF24L01_ADDRSIZE] = NRF24L01_ADDRP4;
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static uint8_t nrf24l01_addr5[NRF24L01_ADDRSIZE] = NRF24L01_ADDRP5;
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static uint8_t nrf24l01_addrtx[NRF24L01_ADDRSIZE] = NRF24L01_ADDRTX;
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/*
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* read one register
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*/
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uint8_t nrf24l01_readregister(uint8_t reg) {
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nrf24l01_CSNlo; //low CSN
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spi_writereadbyte(NRF24L01_CMD_R_REGISTER | (NRF24L01_CMD_REGISTER_MASK & reg));
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uint8_t result = spi_writereadbyte(NRF24L01_CMD_NOP); //read write register
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nrf24l01_CSNhi; //high CSN
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return result;
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}
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/*
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* read many registers
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*/
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void nrf24l01_readregisters(uint8_t reg, uint8_t *value, uint8_t len) {
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uint8_t i = 0;
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nrf24l01_CSNlo; //low CSN
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spi_writereadbyte(NRF24L01_CMD_R_REGISTER | (NRF24L01_CMD_REGISTER_MASK & reg));
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for(i=0; i<len; i++)
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value[i] = spi_writereadbyte(NRF24L01_CMD_NOP); //read write register
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nrf24l01_CSNhi; //high CSN
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}
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/*
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* write one register
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*/
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void nrf24l01_writeregister(uint8_t reg, uint8_t value) {
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nrf24l01_CSNlo; //low CSN
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spi_writereadbyte(NRF24L01_CMD_W_REGISTER | (NRF24L01_CMD_REGISTER_MASK & reg));
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spi_writereadbyte(value); //write register
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nrf24l01_CSNhi; //high CSN
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}
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/*
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* write many registers
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*/
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void nrf24l01_writeregisters(uint8_t reg, uint8_t *value, uint8_t len) {
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uint8_t i = 0;
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nrf24l01_CSNlo; //low CSN
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spi_writereadbyte(NRF24L01_CMD_W_REGISTER | (NRF24L01_CMD_REGISTER_MASK & reg));
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for(i=0; i<len; i++)
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spi_writereadbyte(value[i]); //write register
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nrf24l01_CSNhi; //high CSN
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}
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/*
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* reverse an array, NRF24L01 expects LSB first
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*/
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void nrf24l01_revaddress(uint8_t *addr, uint8_t *addrrev) {
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//reverse address
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uint8_t i = 0;
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for(i=0; i<NRF24L01_ADDRSIZE; i++)
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memcpy(&addrrev[i], &addr[NRF24L01_ADDRSIZE-1-i], 1);
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}
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/*
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* set rx address
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*/
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void nrf24l01_setrxaddr(uint8_t pipe, uint8_t *addr) {
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if(pipe == 0) {
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memcpy(&nrf24l01_addr0, addr, NRF24L01_ADDRSIZE); //cache address
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uint8_t addrrev[NRF24L01_ADDRSIZE];
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nrf24l01_revaddress(addr, (uint8_t *)addrrev);
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nrf24l01_writeregisters(NRF24L01_REG_RX_ADDR_P0, addrrev, NRF24L01_ADDRSIZE);
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} else if(pipe == 1) {
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memcpy(&nrf24l01_addr1, addr, NRF24L01_ADDRSIZE); //cache address
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uint8_t addrrev[NRF24L01_ADDRSIZE];
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nrf24l01_revaddress(addr, (uint8_t *)addrrev);
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nrf24l01_writeregisters(NRF24L01_REG_RX_ADDR_P1, addrrev, NRF24L01_ADDRSIZE);
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} else if(pipe == 2) {
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memcpy(&nrf24l01_addr2, addr, NRF24L01_ADDRSIZE); //cache address
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nrf24l01_writeregister(NRF24L01_REG_RX_ADDR_P2, addr[NRF24L01_ADDRSIZE-1]); //write only LSB MSBytes are equal to RX_ADDR_P
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} else if(pipe == 3) {
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memcpy(&nrf24l01_addr3, addr, NRF24L01_ADDRSIZE); //cache address
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nrf24l01_writeregister(NRF24L01_REG_RX_ADDR_P3, addr[NRF24L01_ADDRSIZE-1]); //write only LSB MSBytes are equal to RX_ADDR_P
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} else if(pipe == 4) {
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memcpy(&nrf24l01_addr4, addr, NRF24L01_ADDRSIZE); //cache address
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nrf24l01_writeregister(NRF24L01_REG_RX_ADDR_P4, addr[NRF24L01_ADDRSIZE-1]); //write only LSB MSBytes are equal to RX_ADDR_P
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} else if(pipe == 5) {
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memcpy(&nrf24l01_addr5, addr, NRF24L01_ADDRSIZE); //cache address
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nrf24l01_writeregister(NRF24L01_REG_RX_ADDR_P5, addr[NRF24L01_ADDRSIZE-1]); //write only LSB MSBytes are equal to RX_ADDR_P
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}
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}
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/*
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* set tx address
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*/
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void nrf24l01_settxaddr(uint8_t *addr) {
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memcpy(&nrf24l01_addrtx, addr, NRF24L01_ADDRSIZE); //cache address
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uint8_t addrrev[NRF24L01_ADDRSIZE];
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nrf24l01_revaddress(addr, (uint8_t *)addrrev);
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nrf24l01_writeregisters(NRF24L01_REG_RX_ADDR_P0, addrrev, NRF24L01_ADDRSIZE); //set rx address for ack on pipe 0
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nrf24l01_writeregisters(NRF24L01_REG_TX_ADDR, addrrev, NRF24L01_ADDRSIZE); //set tx address
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}
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/*
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* flush RX fifo
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*/
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void nrf24l01_flushRXfifo() {
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nrf24l01_CSNlo; //low CSN
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spi_writereadbyte(NRF24L01_CMD_FLUSH_RX);
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nrf24l01_CSNhi; //high CSN
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}
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/*
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* flush RX fifo
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*/
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void nrf24l01_flushTXfifo() {
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nrf24l01_CSNlo; //low CSN
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spi_writereadbyte(NRF24L01_CMD_FLUSH_TX);
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nrf24l01_CSNhi; //high CSN
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}
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/*
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* set chip as RX
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*/
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void nrf24l01_setRX() {
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nrf24l01_setrxaddr(0, nrf24l01_addr0); //restore pipe 0 address
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nrf24l01_writeregister(NRF24L01_REG_CONFIG, nrf24l01_readregister(NRF24L01_REG_CONFIG) | (1<<NRF24L01_REG_PRIM_RX)); //prx mode
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nrf24l01_writeregister(NRF24L01_REG_CONFIG, nrf24l01_readregister(NRF24L01_REG_CONFIG) | (1<<NRF24L01_REG_PWR_UP)); //power up
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nrf24l01_writeregister(NRF24L01_REG_STATUS, (1<<NRF24L01_REG_RX_DR) | (1<<NRF24L01_REG_TX_DS) | (1<<NRF24L01_REG_MAX_RT)); //reset status
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nrf24l01_flushRXfifo(); //flush rx fifo
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nrf24l01_flushTXfifo(); //flush tx fifo
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nrf24l01_CEhi; //start listening
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_delay_us(150); //wait for the radio to power up
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}
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/*
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* set chip as TX
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*/
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void nrf24l01_setTX() {
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nrf24l01_CElo; //stop listening
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nrf24l01_writeregister(NRF24L01_REG_CONFIG, nrf24l01_readregister(NRF24L01_REG_CONFIG) & ~(1<<NRF24L01_REG_PRIM_RX)); //ptx mode
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nrf24l01_writeregister(NRF24L01_REG_CONFIG, nrf24l01_readregister(NRF24L01_REG_CONFIG) | (1<<NRF24L01_REG_PWR_UP)); //power up
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nrf24l01_writeregister(NRF24L01_REG_STATUS, (1<<NRF24L01_REG_RX_DR) | (1<<NRF24L01_REG_TX_DS) | (1<<NRF24L01_REG_MAX_RT)); //reset status
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nrf24l01_flushTXfifo(); //flush tx fifo
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_delay_us(150); //wait for the radio to power up
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}
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#if NRF24L01_PRINTENABLE == 1
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/*
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* print info
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*/
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void nrf24l01_printinfo(void(*prints)(const char *), void(*printc)(unsigned char data)) {
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char buff[100];
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prints("info\r\n");
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sprintf(buff,"STATUS: %02X\r\n", nrf24l01_getstatus()); prints(buff);
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sprintf(buff,"CONFIG: %02X\r\n", nrf24l01_readregister(NRF24L01_REG_CONFIG)); prints(buff);
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sprintf(buff,"RF_CH: %02X\r\n", nrf24l01_readregister(NRF24L01_REG_RF_CH)); prints(buff);
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sprintf(buff,"RF_SETUP: %02X\r\n", nrf24l01_readregister(NRF24L01_REG_RF_SETUP)); prints(buff);
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sprintf(buff,"EN_AA: %02X\r\n", nrf24l01_readregister(NRF24L01_REG_EN_AA)); prints(buff);
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sprintf(buff,"EN_RXADDR: %02X\r\n", nrf24l01_readregister(NRF24L01_REG_EN_RXADDR)); prints(buff);
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sprintf(buff,"OBSERVE_TX: %02X\r\n", nrf24l01_readregister(NRF24L01_REG_OBSERVE_TX)); prints(buff);
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prints("\r\n");
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}
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#endif
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/*
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* get status register
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*/
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uint8_t nrf24l01_getstatus() {
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uint8_t status = 0;
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nrf24l01_CSNlo; //low CSN
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status = spi_writereadbyte(NRF24L01_CMD_NOP); //get status, send NOP request
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nrf24l01_CSNhi; //high CSN
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return status;
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}
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/*
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* check if there is data ready
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*/
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uint8_t nrf24l01_readready(uint8_t* pipe) {
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uint8_t status = nrf24l01_getstatus();
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uint8_t ret = status & (1<<NRF24L01_REG_RX_DR);
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if(ret) {
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//get the pipe number
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if(pipe)
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*pipe = (status >> NRF24L01_REG_RX_P_NO) & 0b111;
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}
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return ret;
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}
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/*
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* get data
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*/
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void nrf24l01_read(uint8_t *data) {
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uint8_t i = 0;
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//read rx register
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nrf24l01_CSNlo; //low CSN
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spi_writereadbyte(NRF24L01_CMD_R_RX_PAYLOAD);
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for(i=0; i<NRF24L01_PAYLOAD; i++)
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data[i] = spi_writereadbyte(NRF24L01_CMD_NOP);
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nrf24l01_CSNhi; //high CSN
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//reset register
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nrf24l01_writeregister(NRF24L01_REG_STATUS, (1<<NRF24L01_REG_RX_DR));
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//handle ack payload receipt
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if (nrf24l01_getstatus() & (1<<NRF24L01_REG_TX_DS))
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nrf24l01_writeregister(NRF24L01_REG_STATUS, (1<<NRF24L01_REG_TX_DS));
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}
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/*
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* put data
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*/
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uint8_t nrf24l01_write(uint8_t *data) {
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uint8_t i = 0;
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uint8_t ret = 0;
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//set tx mode
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nrf24l01_setTX();
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//write data
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nrf24l01_CSNlo; //low CSN
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spi_writereadbyte(NRF24L01_CMD_W_TX_PAYLOAD);
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for (i=0; i<NRF24L01_PAYLOAD; i++)
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spi_writereadbyte(data[i]);
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nrf24l01_CSNhi; //high CSN
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//start transmission
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nrf24l01_CEhi; //high CE
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_delay_us(15);
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nrf24l01_CElo; //low CE
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//stop if max_retries reached or send is ok
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do {
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_delay_us(10);
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}
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while( !(nrf24l01_getstatus() & (1<<NRF24L01_REG_MAX_RT | 1<<NRF24L01_REG_TX_DS)) );
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if(nrf24l01_getstatus() & 1<<NRF24L01_REG_TX_DS)
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ret = 1;
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//reset PLOS_CNT
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nrf24l01_writeregister(NRF24L01_REG_RF_CH, NRF24L01_CH);
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//power down
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nrf24l01_writeregister(NRF24L01_REG_CONFIG, nrf24l01_readregister(NRF24L01_REG_CONFIG) & ~(1<<NRF24L01_REG_PWR_UP));
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//set rx mode
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nrf24l01_setRX();
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return ret;
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}
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/*
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* set power level
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*/
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void nrf24l01_setpalevel() {
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uint8_t setup = nrf24l01_readregister(NRF24L01_REG_RF_SETUP);
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setup &= ~((1<<NRF24L01_REG_RF_PWR_LOW) | (1<<NRF24L01_REG_RF_PWR_HIGH));
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if (NRF24L01_RF24_PA == NRF24L01_RF24_PA_MAX) {
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setup |= (1<<NRF24L01_REG_RF_PWR_LOW) | (1<<NRF24L01_REG_RF_PWR_HIGH);
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} else if (NRF24L01_RF24_PA == NRF24L01_RF24_PA_HIGH) {
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setup |= (1<<NRF24L01_REG_RF_PWR_HIGH) ;
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} else if (NRF24L01_RF24_PA == NRF24L01_RF24_PA_LOW) {
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setup |= (1<<NRF24L01_REG_RF_PWR_LOW);
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} else if (NRF24L01_RF24_PA == NRF24L01_RF24_PA_MIN) {
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} else {
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//default is max power
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setup |= (1<<NRF24L01_REG_RF_PWR_LOW) | (1<<NRF24L01_REG_RF_PWR_HIGH);
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}
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nrf24l01_writeregister(NRF24L01_REG_RF_SETUP, setup);
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}
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/*
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* set datarate
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*/
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void nrf24l01_setdatarate() {
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uint8_t setup = nrf24l01_readregister(NRF24L01_REG_RF_SETUP) ;
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setup &= ~((1<<NRF24L01_REG_RF_DR_LOW) | (1<<NRF24L01_REG_RF_DR_HIGH));
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if(NRF24L01_RF24_SPEED == NRF24L01_RF24_SPEED_250KBPS) {
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setup |= (1<<NRF24L01_REG_RF_DR_LOW);
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} else {
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if (NRF24L01_RF24_SPEED == NRF24L01_RF24_SPEED_2MBPS) {
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setup |= (1<<NRF24L01_REG_RF_DR_HIGH);
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} else if (NRF24L01_RF24_SPEED == NRF24L01_RF24_SPEED_2MBPS) {
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} else {
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//default is 1Mbps
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}
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}
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nrf24l01_writeregister(NRF24L01_REG_RF_SETUP, setup);
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}
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/*
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* set crc length
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*/
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void nrf24l01_setcrclength() {
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uint8_t config = nrf24l01_readregister(NRF24L01_REG_CONFIG) & ~((1<<NRF24L01_REG_CRCO) | (1<<NRF24L01_REG_EN_CRC));
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if (NRF24L01_RF24_CRC == NRF24L01_RF24_CRC_DISABLED) {
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//nothing
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} else if (NRF24L01_RF24_CRC == NRF24L01_RF24_CRC_8) {
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config |= (1<<NRF24L01_REG_EN_CRC);
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} else if (NRF24L01_RF24_CRC == NRF24L01_RF24_CRC_16) {
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config |= (1<<NRF24L01_REG_EN_CRC);
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config |= (1<<NRF24L01_REG_CRCO);
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} else {
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//default is disabled
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}
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nrf24l01_writeregister(NRF24L01_REG_CONFIG, config);
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}
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/*
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* init nrf24l01
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*/
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void nrf24l01_init() {
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//setup port
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NRF24L01_DDR |= (1<<NRF24L01_CSN); //output
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NRF24L01_DDR |= (1<<NRF24L01_CE); //output
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spi_init(); //init spi
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nrf24l01_CElo; //low CE
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nrf24l01_CSNhi; //high CSN
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_delay_ms(5); //wait for the radio to init
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nrf24l01_setpalevel(); //set power level
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nrf24l01_setdatarate(); //set data rate
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nrf24l01_setcrclength(); //set crc length
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nrf24l01_writeregister(NRF24L01_REG_SETUP_RETR, NRF24L01_RETR); // set retries
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nrf24l01_writeregister(NRF24L01_REG_DYNPD, 0); //disable dynamic payloads
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nrf24l01_writeregister(NRF24L01_REG_RF_CH, NRF24L01_CH); //set RF channel
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//payload size
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#if NRF24L01_ENABLEDP0 == 1
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nrf24l01_writeregister(NRF24L01_REG_RX_PW_P0, NRF24L01_PAYLOAD);
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#endif
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#if NRF24L01_ENABLEDP1 == 1
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nrf24l01_writeregister(NRF24L01_REG_RX_PW_P1, NRF24L01_PAYLOAD);
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#endif
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#if NRF24L01_ENABLEDP2 == 1
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nrf24l01_writeregister(NRF24L01_REG_RX_PW_P2, NRF24L01_PAYLOAD);
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#endif
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#if NRF24L01_ENABLEDP3 == 1
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nrf24l01_writeregister(NRF24L01_REG_RX_PW_P3, NRF24L01_PAYLOAD);
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#endif
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#if NRF24L01_ENABLEDP4 == 1
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nrf24l01_writeregister(NRF24L01_REG_RX_PW_P4, NRF24L01_PAYLOAD);
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#endif
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#if NRF24L01_ENABLEDP5 == 1
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nrf24l01_writeregister(NRF24L01_REG_RX_PW_P5, NRF24L01_PAYLOAD);
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#endif
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//enable pipe
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nrf24l01_writeregister(NRF24L01_REG_EN_RXADDR, 0);
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#if NRF24L01_ENABLEDP0 == 1
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nrf24l01_writeregister(NRF24L01_REG_EN_RXADDR, nrf24l01_readregister(NRF24L01_REG_EN_RXADDR) | (1<<NRF24L01_REG_ERX_P0));
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#endif
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#if NRF24L01_ENABLEDP1 == 1
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nrf24l01_writeregister(NRF24L01_REG_EN_RXADDR, nrf24l01_readregister(NRF24L01_REG_EN_RXADDR) | (1<<NRF24L01_REG_ERX_P1));
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#endif
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#if NRF24L01_ENABLEDP2 == 1
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nrf24l01_writeregister(NRF24L01_REG_EN_RXADDR, nrf24l01_readregister(NRF24L01_REG_EN_RXADDR) | (1<<NRF24L01_REG_ERX_P2));
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#endif
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#if NRF24L01_ENABLEDP3 == 1
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nrf24l01_writeregister(NRF24L01_REG_EN_RXADDR, nrf24l01_readregister(NRF24L01_REG_EN_RXADDR) | (1<<NRF24L01_REG_ERX_P3));
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#endif
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#if NRF24L01_ENABLEDP4 == 1
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nrf24l01_writeregister(NRF24L01_REG_EN_RXADDR, nrf24l01_readregister(NRF24L01_REG_EN_RXADDR) | (1<<NRF24L01_REG_ERX_P4));
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#endif
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#if NRF24L01_ENABLEDP5 == 1
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nrf24l01_writeregister(NRF24L01_REG_EN_RXADDR, nrf24l01_readregister(NRF24L01_REG_EN_RXADDR) | (1<<NRF24L01_REG_ERX_P5));
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#endif
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//auto ack
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#if NRF24L01_ACK == 1
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) | (1<<NRF24L01_REG_ENAA_P0));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) | (1<<NRF24L01_REG_ENAA_P1));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) | (1<<NRF24L01_REG_ENAA_P2));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) | (1<<NRF24L01_REG_ENAA_P3));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) | (1<<NRF24L01_REG_ENAA_P4));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) | (1<<NRF24L01_REG_ENAA_P5));
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#else
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) & ~(1<<NRF24L01_REG_ENAA_P0));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) & ~(1<<NRF24L01_REG_ENAA_P1));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) & ~(1<<NRF24L01_REG_ENAA_P2));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) & ~(1<<NRF24L01_REG_ENAA_P3));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) & ~(1<<NRF24L01_REG_ENAA_P4));
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nrf24l01_writeregister(NRF24L01_REG_EN_AA, nrf24l01_readregister(NRF24L01_REG_EN_AA) & ~(1<<NRF24L01_REG_ENAA_P5));
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#endif
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//rx address
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nrf24l01_setrxaddr(0, nrf24l01_addr0);
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nrf24l01_setrxaddr(1, nrf24l01_addr1);
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nrf24l01_setrxaddr(2, nrf24l01_addr2);
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nrf24l01_setrxaddr(3, nrf24l01_addr3);
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nrf24l01_setrxaddr(4, nrf24l01_addr4);
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nrf24l01_setrxaddr(5, nrf24l01_addr5);
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//tx address
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nrf24l01_settxaddr(nrf24l01_addrtx);
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//set rx mode
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nrf24l01_setRX();
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}
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