93 lines
3.0 KiB
C
93 lines
3.0 KiB
C
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/*
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nrf24l01 lib 0x02
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copyright (c) Davide Gironi, 2012
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Released under GPLv3.
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Please refer to LICENSE file for licensing information.
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*/
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/* Memory Map */
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#define NRF24L01_REG_CONFIG 0x00
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#define NRF24L01_REG_EN_AA 0x01
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#define NRF24L01_REG_EN_RXADDR 0x02
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#define NRF24L01_REG_SETUP_AW 0x03
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#define NRF24L01_REG_SETUP_RETR 0x04
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#define NRF24L01_REG_RF_CH 0x05
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#define NRF24L01_REG_RF_SETUP 0x06
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#define NRF24L01_REG_STATUS 0x07
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#define NRF24L01_REG_OBSERVE_TX 0x08
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#define NRF24L01_REG_CD 0x09
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#define NRF24L01_REG_RX_ADDR_P0 0x0A
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#define NRF24L01_REG_RX_ADDR_P1 0x0B
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#define NRF24L01_REG_RX_ADDR_P2 0x0C
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#define NRF24L01_REG_RX_ADDR_P3 0x0D
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#define NRF24L01_REG_RX_ADDR_P4 0x0E
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#define NRF24L01_REG_RX_ADDR_P5 0x0F
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#define NRF24L01_REG_TX_ADDR 0x10
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#define NRF24L01_REG_RX_PW_P0 0x11
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#define NRF24L01_REG_RX_PW_P1 0x12
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#define NRF24L01_REG_RX_PW_P2 0x13
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#define NRF24L01_REG_RX_PW_P3 0x14
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#define NRF24L01_REG_RX_PW_P4 0x15
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#define NRF24L01_REG_RX_PW_P5 0x16
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#define NRF24L01_REG_FIFO_STATUS 0x17
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#define NRF24L01_REG_FEATURE 0x1D
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#define NRF24L01_REG_DYNPD 0x1C
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/* Bit Mnemonics */
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#define NRF24L01_REG_MASK_RX_DR 6
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#define NRF24L01_REG_MASK_TX_DS 5
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#define NRF24L01_REG_MASK_MAX_RT 4
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#define NRF24L01_REG_EN_CRC 3
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#define NRF24L01_REG_CRCO 2
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#define NRF24L01_REG_PWR_UP 1
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#define NRF24L01_REG_PRIM_RX 0
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#define NRF24L01_REG_ENAA_P5 5
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#define NRF24L01_REG_ENAA_P4 4
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#define NRF24L01_REG_ENAA_P3 3
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#define NRF24L01_REG_ENAA_P2 2
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#define NRF24L01_REG_ENAA_P1 1
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#define NRF24L01_REG_ENAA_P0 0
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#define NRF24L01_REG_ERX_P5 5
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#define NRF24L01_REG_ERX_P4 4
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#define NRF24L01_REG_ERX_P3 3
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#define NRF24L01_REG_ERX_P2 2
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#define NRF24L01_REG_ERX_P1 1
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#define NRF24L01_REG_ERX_P0 0
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#define NRF24L01_REG_AW 0
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#define NRF24L01_REG_ARD 4
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#define NRF24L01_REG_ARC 0
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#define NRF24L01_REG_PLL_LOCK 4
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#define NRF24L01_REG_RF_DR 3
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#define NRF24L01_REG_RF_PWR 1
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#define NRF24L01_REG_LNA_HCURR 0
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#define NRF24L01_REG_RX_DR 6
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#define NRF24L01_REG_TX_DS 5
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#define NRF24L01_REG_MAX_RT 4
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#define NRF24L01_REG_RX_P_NO 1
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#define NRF24L01_REG_TX_FULL 0
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#define NRF24L01_REG_PLOS_CNT 4
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#define NRF24L01_REG_ARC_CNT 0
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#define NRF24L01_REG_TX_REUSE 6
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#define NRF24L01_REG_FIFO_FULL 5
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#define NRF24L01_REG_TX_EMPTY 4
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#define NRF24L01_REG_RX_FULL 1
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#define NRF24L01_REG_RX_EMPTY 0
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#define NRF24L01_REG_RPD 0x09
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#define NRF24L01_REG_RF_DR_LOW 5
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#define NRF24L01_REG_RF_DR_HIGH 3
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#define NRF24L01_REG_RF_PWR_LOW 1
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#define NRF24L01_REG_RF_PWR_HIGH 2
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/* Instruction Mnemonics */
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#define NRF24L01_CMD_R_REGISTER 0x00
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#define NRF24L01_CMD_W_REGISTER 0x20
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#define NRF24L01_CMD_REGISTER_MASK 0x1F
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#define NRF24L01_CMD_R_RX_PAYLOAD 0x61
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#define NRF24L01_CMD_W_TX_PAYLOAD 0xA0
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#define NRF24L01_CMD_FLUSH_TX 0xE1
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#define NRF24L01_CMD_FLUSH_RX 0xE2
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#define NRF24L01_CMD_REUSE_TX_PL 0xE3
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#define NRF24L01_CMD_NOP 0xFF
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